1. Field of the Invention
The present invention relates to an AD converter and its control method and, and more particularly to an AD converter with a power saving circuit and its control method.
2. Description of the Related Art
FIG. 5 shows an example of the configuration of a conventional AD converter with sampling capacitors.
An AD converter 501 comprises an analog input side capacitor array 502, a reference side capacitor array 503, a comparator 504, and a successive approximation control circuit 505. The analog input side capacitor array 502 is an array composed of 4-bit-weighted capacitors 508, 509, 510, 511, and 512. That is, the capacitors 508 and 509 are capacitors with the reference capacity value of C, the capacity 510 is a capacitor with the capacity value of 2C, the capacity 511 is a capacitor with the capacity value of 4C, and the capacity 512 is a capacitor with the capacity value of 8C. The one end of each of the above capacitors is connected to a selector 518, 519, 520, 521, or 522, respectively and, in response to a control signal 534 from the successive approximation control circuit 505, is connected to an analog input terminal 536, a reference power source terminal 537, or a ground terminal 538.
The reference side capacitor array 503 is also an array composed of 4-bit-weighted capacitors 513, 514, 515, 516, and 517. That is, the capacitors 513 and 514 are capacitors with the reference capacity value of C, the capacity 515 is a capacitor with the capacity value of 2C, the capacity 516 is a capacitor with the capacity value of 4C, and the capacity 517 is a capacitor with the capacity value of 8C. The one end of each of the above capacitors is connected to a selector 523, 524, 525, 526, or 527, respectively and, in response to the control signal 534 from the successive approximation control circuit 505, is connected to a ground terminal 539.
The comparator 504 comprises an output-stage amplifier 543 and a pre-amplifier 542 that reduces the offset of the output-stage amplifier 543. The output-stage amplifier 543 and the pre-amplifier 542 are connected via offset-canceling capacitors 545 and 546. Analog switch 547 and 548, provided for determining the operation point of the output-stage amplifier 543 and for canceling the offset of the pre-amplifier 542, are turned on during offset canceling.
Switches 530 and 531 are switches used to fix the potential of a common electrodes 532 of the analog input side capacitor array 502 and a common electrode 533 of the reference side capacitor array 503, respectively, to the intermediate potential 541 output from a bias circuit 540 when sampling the analog input voltage.
Next, the AD conversion operation of the conventional AD converter shown in FIG. 5 will be described.
First, in the sampling mode, switches 530 and 531 are turned on. Then, the common electrode 532 of the analog input side capacitor array 502 and the common electrode 533 of the reference side capacitor array 503 are connected to the intermediate potential 541 output from the bias circuit 540. The capacitors 508-512 are connected to the analog input voltage VAIN by the selectors 518-522. The capacitors 513-517 are connected to the ground potential GND by the selectors 523-527. Turning the switches 547 and 548 on sets inputs 549 and 550 of the output-stage amplifier 543 to the intermediate potential 541 output from the bias circuit 540 and, at the same time, stores the output offset of the pre-amplifier 542 in the offset-canceling capacitors 545 and 546. At this time, let VS be the intermediate potential 541 output from the bias circuit 540. Then, the total charge Q13 accumulated in the analog input side capacitor array 502 is calculated as:
Q13=16Cxc3x97(VAINxe2x88x92VS)xe2x80x83xe2x80x83(25)
The total charge Q14 accumulated in the reference side capacitor array 503 is calculated as:
Q14=16Cxc3x97(xe2x88x92VS)xe2x80x83xe2x80x83(26)
Next, when the mode is changed to the comparison mode, switches 530 and 531 are turned off. Then, the capacitors 508-511 are connected to the ground potential GND by selectors 518-521. The capacitor 512 is connected to the reference potential VR by the selector 522. The capacitors 513-517 are connected to the ground potential GND by the selectors 523-527. At this time, let VCM1 be the potential of the common electrode 532. Then, the total charge Q15 accumulated in the analog input side capacitor array 502 is calculated as:
xe2x80x83Q15=8Cxc3x97(VRxe2x88x92VCM1)xe2x88x928Cxc3x97VCM1xe2x80x83xe2x80x83(27)
Let VCM2 be the potential of the common electrode 533. Then, the total charge Q16 accumulated in the reference side capacitor array 503 is calculated as:
Q16=16Cxc3x97(xe2x88x92VCM2)xe2x80x83xe2x80x83(28)
Here,
Q13=Q15xe2x80x83xe2x80x83(29)
Q14=Q16xe2x80x83xe2x80x83(30)
by the law of charge conservation. The following is obtained by substituting equations (25)-(28) into equations (29) and (30):
VCM1=xc2xdxc3x97VRxe2x88x92VAIN+VSxe2x80x83xe2x80x83(31)
VCM2=VSxe2x80x83xe2x80x83(32)
The comparator 504 outputs the comparison result of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d by comparing the potential VCM1 of the common electrode 532 represented by equation (31) with the potential VCM2 of the common electrode 533 represented by equation (32). As equations (31) and (32) show, when the analog input voltage VAIN equals the output voltage of the analog input side capacitor array (here, xc2xdxc3x97VR), both the potentials VCM1 and VCM2 of the comparator side electrodes become VS as if the offset of the pre-amplifier 542 was canceled. The output offset of the pre-amplifier 542, generated when the potential of the common electrodes 532 and 533 which are the inputs to the pre-amplifier 542 is VS, is accumulated in the offset-canceling capacitors 545 and 546. Therefore, the potential of the inputs 549 and 550 of the output-stage amplifier 543 also become VS, and therefore the output offset of the pre-amplifier 542 may be ignored. The input offset of the output-stage amplifier 543 is reduced to a value generated by dividing it by the amplification ratio of the pre-amplifier 542.
The successive approximation control circuit 505 determines the value of the most significant bit of the conversion result based on the output from the comparator 504, and supplies the control signal 534 to the selectors 518-522 to perform the comparison operation corresponding to the bit in the next place.
If the analog input voltage VAIN is higher than xc2xdxc3x97VR, the comparator 504 outputs xe2x80x9c1xe2x80x9d to output the control signal 534 to connect the capacitor 511, corresponding to the bit in the next place, to the reference voltage VR while the capacitor 512, corresponding to the most-significant bit, is still connected to the reference voltage VR. That is, in the second comparison, the analog input voltage VAIN is compared with xc2xexc3x97VR. Conversely, if the analog input voltage VAIN is lower than xc2xdxc3x97VR, the comparator 504 outputs xe2x80x9c0xe2x80x9d to output the control signal 534 to connect the capacitor 512, corresponding to the most significant bit, to the ground potential GND and to connect the capacitor 511, corresponding to the bit in the next place, to the reference voltage VR. In the second comparison, the analog input voltage VAIN is compared with xc2xcxc3x97VR. In this way, by repeating the operation in which the successive approximation control circuit 505 outputs the successive approximation control signal 534 and then determines the bit value based on the output of the comparator 504 for a specified number of times (four times in this example), the analog input voltage VAIN is converted to digital output signals 535.
However, this prior art has the following problems:
The first problem is that the output voltage of the bias circuit has some limitations. The following describes the reason. To perform the normal AD conversion operation in the AD converter described above, it is necessary to conserve the charge of the common electrode 532 in the comparison mode. In this case, if the input impedance is extremely high as in the comparator where an MOS transistor is used in the input stage, there is no problem. However, there is a charge leak problem caused by the switch 530 connected to the common electrode 532. Now, consider a CMOS analog switch in which an N-channel transistor 601 and a P-channel transistor 602 are connected in parallel and complementary switch control signals 603 and 604 are sent to the gates, as shown in FIG. 6.
FIG. 7 shows an equivalent circuit of the CMOS analog switch shown in FIG. 6.
As shown in FIG. 7, the CMOS analog switch has parasitic diodes. Diodes 703 and 704 are parasitic diodes between the drain/source diffusion layer and the P-well or P-substrate of the N-channel transistor 601. Because the P-well or P-substrate is normally at the ground potential GND, the ground potential GND is connected to one end of each of the diodes 703 and 704. Diodes 701 and 702 are parasitic diodes between the drain/source diffusion layer and the N-well or N-substrate of the P-channel transistor 602. Because the N-well or N-substrate is normally at the power source potential VDD, the power source potential VDD is connected to one end of each of the diodes 701 and 702. In addition, a resistor 709 is an equivalent resistor when the switch is turned on, capacitors 705 and 706 are a parasitic capacity between the gate and the source, and a parasitic capacity between the gate and the drain, of the P-channel transistor 602, and capacitors 707 and 708 are a parasitic capacity between the gate and the source, and a parasitic capacity between the gate and the drain, of the N-channel transistor 601.
The potential VCM1 of the common electrode 532 is represented by equation (31) when the AD converter 501 is in the comparison mode of the most significant bit. Therefore, when the analog input voltage VAIN is near the power source potential or the ground potential, the potential VCM1 of the common electrode 532 is sometimes higher than the power source potential or lower than the ground potential. When the potential VCM1 of the common electrode 532 is out of the power source voltage range, one of the parasitic diodes 701-704 in the switch 530 conducts and the charge accumulated in the common electrode 532 leaks through the conducting diode, preventing the normal AD conversion operation. To prevent this, it is found that, from equation (31),
VS=xc2xdxc3x97VDDxe2x80x83xe2x80x83(33)
is necessary. As described above, the conventional AD converter imposes limitations on the output voltage of the bias circuit.
The second problem is that the low-voltage operation is difficult.
The reason is that the ON resistance of the CMOS analog switch is very high when conducting at a voltage near xc2xdxc3x97VDD. This condition becomes more significant as the voltage is decreased. FIG. 8 shows how the ON resistance of the ON resistor 709 of the CMOS analog switch depends on the voltage. FIG. 8(a) shows the ON resistance when the power source voltage is high, while FIG. 8(b) shows the ON resistance when the power source voltage is low. As shown in FIG. 8, the ON resistance of the CMOS analog switch is high when conducting at a voltage near xc2xdxc3x97VDD and this condition becomes more significant as the power source voltage is decreased. As is pointed out in the first problem, because the output voltage VS of the bias circuit 540 must be xc2xdxc3x97VDD, the switch 530 must be used in a condition in which the ON resistance is very high. In the sampling mode, the time required from the moment the switch 530 is turned on to the moment the potential VCM1 of the common electrode 532 becomes equal to the output voltage VS of the bias circuit 540 depends on the time constant of the total capacity of the capacitor array 502, the ON resistance of the switch 530, and the total resistance of the output resistance of the bias circuit 540. Therefore, when the ON resistance of the switch 530 is very high, the sampling mode operation becomes very long. As a result, the AD conversion time becomes too long to be practical.
The third problem is that the low-power operation is difficult.
The reason is that the conventional AD converter requires a bias source. As is pointed out in the second problem, the sampling mode time depends on the time constant of the total capacity of the capacitor array 502, the ON resistance of the switch 530, and the total resistance of the output resistance of the bias circuit 540. Therefore, to reduce the time required for the sampling mode in order to speed up AD conversion, the output resistance of the bias circuit 540 must be decreased. To decrease the output resistance of the bias circuit 540 is to increase the current supply ability of the bias circuit 540. This will result in an increase in the power consumption of the bias circuit 540.
In addition, when the comparator is configured such that the pre-amplifier 542 is provided before, and connected to, the output-stage amplifier 543 via capacitors in order to reduce the offset of the comparator 504, a bias source that biases the potential of the offset-canceling capacitors 545 and 546 to the intermediate potential is necessary. Because the output of the pre-amplifier 542 is connected to the other terminal sides of the offset-canceling capacitors, applying the bias to the offset-canceling capacitors with the power source potential causes the output of the pre-amplifier 542 to increase (or decrease) the potential of the inputs 549 and 550 of the output-stage amplifier 543 too much to get out of the power source voltage range. This causes one of the parasitic diodes to conduct and causes the charge accumulated in the offset-canceling capacitors 545 and 546 to leak through the conducting diode, thus preventing the normal AD conversion operation from being executed.
Japanese Patent Laid-Open Publication No. Hei 1-13818 discloses an AD converter which prevents a charge leak from the CMOS analog switch in order to execute the normal AD conversion operation. FIG. 9 shows the AD converter disclosed in Japanese Patent Laid-Open Publication No. Hei 1-13818. An AD converter 901 comprises an analog input side capacitor array 902, a reference side capacitor array 903, a comparator 904, and a successive approximation control circuit 905. The analog input side capacitor array 902 is an array composed of 4-bit-weighted capacitors 908, 909, 910, 911, and 912. That is, the capacitors 908 and 909 are capacitors with the reference capacity value of C, the capacity 910 is a capacitor with the capacity value of 2C, the capacity 911 is a capacitor with the capacity value of 4C, and the capacity 912 is a capacitor with the capacity value of 8C. The one end of each of the above capacitors is connected to a selector 918, 919, 920, 921, or 922, respectively and, in response to a control signal 934 from the successive approximation control circuit 905, is connected to an analog input terminal 936, a reference power source terminal 937, or a ground terminal 938.
The reference side capacitor array 903 is also an array composed of 4-bit-weighted capacitors 913, 914, 915, 916, and 917. That is, the capacitors 913 and 914 are capacitors with the reference capacity value of C, the capacity 915 is a capacitor with the capacity value of 2C, the capacity 916 is a capacitor with the capacity value of 4C, and the capacity 917 is a capacitor with the capacity value of 8C. The one end of each of the above capacitors is connected to a selector 923, 924, 925, 926, or 927, respectively and, in response to the control signal 934 from the successive approximation control circuit 905, is connected to a ground terminal 939 via the above selector.
Switches 930 and 931 set the potential of a common electrodes 932 of the analog input side capacitor array 902 and a common electrode 933 of the reference side capacitor array 903, respectively, to the intermediate potential 941 output from a bias circuit 940 when sampling the analog input voltage.
The AD converter shown in FIG. 9 differs from the AD converter shown in FIG. 5 in that capacitors 906 and 907, each with the capacity value of 8C that is equal to the capacity value of the most significant bit, are added to the capacitor arrays 902 and 903, respectively. The one end of each of the capacitors 906 and 907 is fixed to ground terminals 938 and 939, respectively.
Next, the AD conversion operation of the AD converter disclosed in Japanese Patent Laid-Open Publication No. Hei 1-13818 and shown in FIG. 9 will be described.
First, in the sampling mode, switches 930 and 931 are turned on. Then, the common electrode 932 of the analog input side capacitor array 902 and the common electrode 933 of the reference side capacitor array 903 are connected to the intermediate potential 941 output from the bias circuit 940. The capacitors 908-912 are connected to the analog input voltage VAIN by the selectors 918-922. The capacitors 913-917 are connected to the ground potential GND by the selectors 923-927. At this time, let VS be the intermediate electric potential 941 output from the 940. Then, the total charge Q17 accumulated in the analog input side capacitor array 902 is calculated as:
Q17=16Cxc3x97(VAINxe2x88x92VS)xe2x88x928Cxc3x97VSxe2x80x83xe2x80x83(34)
The total charge Q18 accumulated in the reference side capacitor array 903 is calculated as:
xe2x80x83Q18=24Cxc3x97(xe2x88x92VS)xe2x80x83xe2x80x83(35)
Next, when the mode is changed to the comparison mode, switches 930 and 931 are turned off. Then, the capacitors 908-911 are connected to the ground potential GND by selectors 918-921. The capacitor 912 is connected to the reference potential VR by the selector 922. The capacitors 913-917 are connected to the ground potential GND by the selectors 923-927. At this time, let VCM1 be the potential of the common electrode 932. Then, the total charge Q19 accumulated in the analog input side capacitor array 902 is calculated as:
Q19=8Cxc3x97(VRxe2x88x92VCM1)xe2x88x9216Cxc3x97VCM1xe2x80x83xe2x80x83(36)
Let VCM2 be the potential of the common electrode 933. Then, the total charge Q20 accumulated in the reference side capacitor array 903 is calculated as:
Q20=24Cxc3x97(xe2x88x92VCM2)xe2x80x83xe2x80x83(37)
Here,
Q17=Q19xe2x80x83xe2x80x83(38)
Q18=Q20xe2x80x83xe2x80x83(39)
by the law of charge conservation. The following is obtained by substituting equations (34)-(37) into equations (38) and (39):
VCM1=⅔xc3x97(xc2xdxc3x97VRxe2x88x92VAIN)+VSxe2x80x83xe2x80x83(40)
VCM2=VSxe2x80x83xe2x80x83(41)
The comparator 904 outputs the comparison result of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d by comparing the potential VCM1 of the common electrode 932 represented by equation (40) with the potential VCM2 of the common electrode 933 represented by equation (41). The successive approximation control circuit 905 determines the value of the most significant bit of the conversion result based on the output from the above comparator 904, and supplies the control signal 934 to the selectors 918-922 to perform the comparison operation on the bit corresponding to the next place. In this way, by repeating the operation in which the successive approximation control circuit 905 outputs the successive approximation control signal 934 and then determines the bit value based on the output of the comparator 904 for a specified number of times (four times in this example), the analog input voltage VAIN is converted to an output signal 935.
However, this prior art has the following problems:
The first problem is that the output voltage of the bias circuit has some limitations. The following describes the reason. To perform the normal AD conversion operation in the AD converter described above, it is necessary to conserve the charge of the common electrode 932 in the comparison mode. In this case, if the input impedance is extremely high as in the comparator where an MOS transistor is used in the input stage, there is no problem. However, there is a charge leak problem caused by the switch 930 connected to the common electrode 932. Now, consider a CMOS analog switch in which an N-channel transistor 601 and a P-channel transistor 602 are connected in parallel and complementary switch control signals 603 and 604 are sent to the gates, as shown in FIG. 6.
As with the conventional AD converter, the potential VCM1 of the common electrode 932 is represented by equation (40) when the AD converter 901 is in the comparison mode of the most significant bit. Therefore, when the analog input voltage VAIN is near the power source potential or the ground potential, the potential VCM1 of the common electrode 932 is sometimes higher than the power source potential or lower than the ground potential.
When the potential VCM1 of the common electrode 932 is out of the power source voltage range, one of the parasitic diodes 701-704 in the switch 930 conducts and the charge accumulated in the common electrode 932 leaks through the conducting diode, preventing the normal AD conversion operation.
To prevent this, it is found that, from equation (40),
VS=⅓xc3x97VDD to ⅔xc3x97VDDxe2x80x83xe2x80x83(42)
is necessary.
As described above, the conventional AD converter imposes limitations on the output voltage of the bias circuit.
The second problem is that the low-voltage operation is difficult.
The reason is that, as with the conventional AD converter, the ON resistance of the CMOS analog switch is very high when conducting at a voltage near xc2xdxc3x97VDD. This condition becomes more significant as the voltage is decreased. As shown in FIG. 8, the ON resistance of the CMOS analog switch is high when conducting at a voltage near xc2xdxc3x97VDD and this condition becomes more significant as the power source voltage is decreased. As is pointed out in the first problem, because the output voltage VS of the bias circuit 940 must be ⅓xc3x97VDD to ⅔xc3x97VDD, the switch 930 must be used in a condition in which the ON resistance is very high. In the sampling mode, the time from the moment the switch 930 is turned on to the moment the potential VCM1 becomes equal to the output voltage VS of the bias circuit 940 depends on the total capacity of the capacitor array 902 and on the time constant of the ON resistance of the switch 930 and the total resistance of the output resistance of the bias circuit 940. Therefore, when the ON resistance of the switch 930 is very high, the sampling mode operation becomes very long. As a result, the AD conversion time becomes too long to be practical.
The third problem is that the low-power operation is difficult.
The reason is that, as with the conventional AD converter, this AD converter also requires a bias source. As is pointed out in the second problem, the sampling mode time depends on the total capacity of the capacitor array 902 and on the time constant of the ON resistance of the switch 930 and the total resistance of the output resistance of the bias circuit 940. Therefore, to reduce the time required for the sampling mode in order to speed up AD conversion, the output resistance of the bias circuit 940 must be decreased. To decrease the output resistance of the bias circuit 940 is to increase the current supply ability of the bias circuit 940. This will result in an increase in the power consumption of the bias circuit 940.
FIG. 10 shows an example of the conventional comparator in which amplifiers are connected via a plurality of capacitors to cancel the offset of the comparator and the input potentials of the amplifiers are set equal during offset cancel operation. A comparator 1001 comprises an output-stage amplifier 1003 and a pre-amplifier 1002 which reduces the offset of the output-stage amplifier 1003. The output-stage amplifier 1003 and the pre-amplifier 1002 are connected via offset-canceling capacitors 1004 and 1005. Analog switches 1012 and 1013, which are provided to set the operation point of the output-stage amplifier 1003 equal to the operation point of the pre-amplifier 1002 and to cancel the offset of the pre-amplifier 1002, are turned on during the offset cancel operation. Analog switches 1015 and 1016 are connected to two inputs 1006 and 1007 of the comparator 1001. An offset canceling bias source 1014 is connected to other side of the analog switches 1015 and 1016.
Next, the operation of the comparator shown in FIG. 10 will be described.
During the offset cancel operation, the analog switches 1015 and 1016 are turned on and the two inputs, 1006 and 1007, of the comparator 1001 are set to an output potential 1017 from the bias source 1014. In addition, the offset canceling switches 1012 and 1013 are turned on, inputs 1010 and 1011 of the output-stage amplifier 1003 are also set to the output potential 1017 of the bias source 1014 and, at the same time, the output offset of the pre-amplifier 1002 is stored in the offset-canceling capacitor 1004 and 1005. During the comparison operation, the offset canceling switches 1012 and 1013 and the analog switches 1015 and 1016 are turned off, the potentials of the two inputs, 1006 and 1007, of the comparator 1001 are compared, and the comparison result 1018 is output. If the potentials of the two inputs, 1006 and 1007, are equal, the output offset of the pre-amplifier 1002 is stored in the offset-canceling capacitors 1004 and 1005. Therefore, the potentials of the inputs 1012 and 1013 of the output-stage amplifier 1003 become equal to the output potential 1017 from the bias source 1014 and therefore the output offset of the pre-amplifier 1002 maybe ignored. The input offset of the output-stage amplifier 1003 is reduced to a value generated by dividing it by the amplification ratio of the pre-amplifier 1002.
However, this prior art has the problems described below.
The first problem is that, when the components of the comparator are arranged close to each other in order to increase the compactor integration density, there is a possibility that the comparator operation will become unstable.
The reason for this will be described below.
In general, to reduce the production cost, a semiconductor integrated circuit is laid out as dense as possible to increase its integration. FIG. 11 schematically shows an example of the layout of the comparator, shown in FIG. 10, including the pre-amplifier 1002, output-stage amplifier 1003, offset canceling capacitor 1005, and offset canceling switch 1013.
To increase the integration, the pre-amplifier 1002, output-stage amplifier 1003, offset canceling capacitor 1005, and offset canceling switch 1013 are arranged close to each other, as shown in FIG. 11. When they are arranged as shown in FIG. 11, the bottom electrode of the offset canceling capacitor 1005 connected to the output 1009 of the pre-amplifier 1002 is placed inevitably near the input 1007 of the comparator 1001 connected to the offset canceling switch 1013. In this state, there is a parasitic capacity 1101 between the input 1007 and the output 1009 of the pre-amplifier 1002 to such a degree that cannot be ignored and, this parasitic capacity 1101 provides the feedback to the pre-amplifier 1002. This feedback sometimes makes the operation of the pre-amplifier 1002 unstable during comparison operation or causes an oscillation. Arranging the components of the comparator close to each other to increase the integration density develops a problem of unstable comparator operation.
It is an object of the present invention to provide an AD converter, as well as its control method, which removes the drawbacks of the prior art described above, reduces the power consumption of the bias source, and makes the high-speed operation possible at a low voltage.
It is anther object of the present invention to provide an AD converter, as well as its control method, which makes possible the stable operation without oscillation even when its components are laid out at a high integration density.
To achieve the above objects, an AD converter according to the present invention basically employs the technical configuration described below.
That is, a first mode of the AD converter according to the present invention is an AD converter in which a first capacitor array is connected to one input of a comparator and a second capacitor array is connected to another input of the comparator and in which a charge proportional to an input analog signal level is accumulated in the first capacitor array, the AD converter comprising:
a level-adjusting capacitor whose one end is connected to the one input of the comparator to adjust a voltage of the one input of the comparator, to which the first capacitor array is connected, to a predetermined voltage; and
switching means for switching a potential of another end of the capacitor to the potential that differs between a sampling mode and a comparison mode.
A second mode is an AD converter in which, in an input signal sampling mode, a first reference capacitor in which a charge proportional to an input analog signal level is accumulated is connected to one input to a comparator and a second reference capacitor is connected to another input of the comparator and in which, in a comparison mode, a predetermined voltage is applied from a resistor array to the first reference capacitor, the AD converter comprising:
a level-adjusting capacitor whose one end is connected to the one input of the comparator to adjust a voltage of the one input of the comparator, to which the first reference capacitor is connected, to a predetermined voltage; and
switching means for switching a potential of another end of the capacitor to the potential that differs between the sampling mode and the comparison mode.
A third mode is the AD converter wherein, in the input signal sampling mode, the switching means is switched to charge an potential of an input side of the comparator to a power source potential.
A fourth mode is the AD converter wherein the power source potential is a ground potential.
A fifth mode is the AD converter wherein the comparator comprises a plurality of amplifiers and capacitors connecting each two of the plurality of amplifiers, wherein at least two stages of switching elements are connected in series to make equal a bias potential of an amplifier in a first stage and the bias potential of each of the amplifiers in a second and following stages, and wherein, at least in the comparison mode, the potential of nodes between the switching elements connected in series is fixed to a predetermined potential.
A sixth mode is the AD converter wherein one of the switching elements makes the potential of the two inputs of the comparator equal to the bias potential of the plurality of amplifiers in the comparator.
A seventh mode is the AD converter wherein the switching means makes the potential of another end of the capacitor a power source potential to make the one input of the comparator a predetermined potential and to cancel an offset of the comparator at the potential.
A first mode of an AD converter control method according to the present invention is a control method in which a first capacitor array is connected to one input of a comparator and a second capacitor array is connected to another input of the comparator and in which a charge proportional to an input analog signal level is accumulated in the first capacitor array, the AD converter control method comprising the steps of:
providing a level-adjusting capacitor whose one end is connected to the one input of the comparator to adjust a voltage of the one input of the comparator, to which the first capacitor array is connected, to a predetermined voltage; and
switching a potential of another end of the capacitor to the potential that differs between a sampling mode and a comparison mode.
A second mode is an AD converter control method in which, in an input signal sampling mode, a first reference capacitor in which a charge proportional to an input analog signal level is accumulated is connected to one input to a comparator and a second reference capacitor is connected to another input of the comparator and in which, in a comparison mode, a predetermined voltage is applied from a resistor array to the first reference capacitor, the AD converter control method comprising the steps of:
providing a level-adjusting capacitor whose one end is connected to the one input of the comparator to adjust a voltage of the one input of the comparator, to which the first reference capacitor is connected, to a predetermined voltage; and
switching a potential of another end of the capacitor to the potential that differs between the sampling mode and the comparison mode.
A third mode is an AD converter control method wherein an offset of the comparator is canceled at a voltage generated by the level-adjusting capacitor.